1. Field of the Invention
This invention relates to circuitry used, e.g., to generate a clock signal in phase synchronization with an input signal thereto, and, more particularly, to circuitry used therein to provide a comparison signal indicating phase relationship between input signal and clock signal.
2. Description of Prior Art
Phase-locked loop circuits are commonly used in digital data systems to provide a data clock locked in phase synchronization with data bits in a serial digital data stream, the data clock being phase-locked to either a separate input clock signal or to the data bits of the data stream itself. In general, a phase detector circuit compares input and clock signals and provides a control signal to a voltage-controlled oscillator (VCO) generating the clock signal. The control signal controls frequency and phase of the clock signal in such a manner that clock and input signals are locked in phase synchronization. An example of such a phase locked loop is shown in Dunn, U.S. Pat. No. 4,069,462, incorporated herein by reference.
When, e.g., data is read out of a rotating magnetic memory, such as a Data General Corporation Model 6063, 6064, or 6065 disc drive unit, the data often appears in a self-clocking code format at variable data rates of up to 7.2 megabits per second. Clock information is contained within the format of the self-clocking code, rather than being provided as a separate signal, and the data clock is phase locked to the data stream. In modified frequency modulation (MFM) code format frequently used in rotating disc memories, the data stream is divided into equal imaginary time intervals, called bit cells. A data pulse will be present in the middle of each bit cell containing a logic 1 data bit, and at the boundary between consecutive bit cells containing logic zero data bits. A property of this coding scheme is that the instantaneous frequency of the data stream, i.e., a frequency related to time interval between consecutive data pulses, lies within a comparatively narrow band of frequencies. If the data rate is F, the lowest instantaneous frequency will be F/2, corresponding to a data stream of 101010, and so on. The highest instantaneous frequency will be F, corresponding to a data stream of 000, and so on, or 111, and so on. There is also an intermediate frequency of 2/3 F, corresponding to a data stream of 100100, and so on. In MFM code, then, input signal frequencies will lie in the band of F/2 to F and will be harmonically related to a frequency twice the data rate.
The phase-locked loop circuit should therefore be capable of harmonic lock to any input signal frequency component. The clock signal should therefore have a frequency at least twice the data rate, but should not have a frequency higher than twice the data rate; it is difficult to obtain adequate performance in VCOs at frequencies more than twice the data rates of modern disc drive units, e.g., 7.2 megabits per second. Additionally, the circuit should not require adjustment of its component values to ensure proper operation. It should not require input or clock signals having well defined pulse widths or shapes, and should be tolerant of variations in data pulse location within bit cells. As a further requirement, the circuit should be capable of reliability and simply decoding MFM coded input signals to provide a data signal output in binary code.
Whether the above requirements are met is primarily a function of the phase detector circuit, and secondarily of the voltage-controlled oscillator. A recurring problem in phase detectors arises from the periodic character of phase error between clock and input signals. Phase error is zero when clock and input signals are in phase and increases to a maximum value as clock signal shifts in time relative to input signal. When the shift equals one complete cycle of input signal, the signals are again in phase and phase error abruptly changes from maximum to zero. Phase error is therefore at the point of switching between minimum and maximum values when clock and input signals are in phase. This condition is unstable, so that the clock signal would tend to oscillate about the point of phase synchronization. Previous phase comparators have avoided this problem, but in doing so have required clock signals four to eight times the input signal frequency or have been dependent upon pulse width and shape.
The present invention provides a solution to these problems of the prior art as will be discussed in detail hereinbelow.